SIL Verification and SIF Design Basics (IEC 61511)

A SIL target is a promise; verification is where it is checked. The course takes the SIF from the safety requirements specification through sensor, logic-solver and final-element selection, failure-rate data, PFDavg calculation, architectural constraints and systematic capability, to the proof-test interval and coverage that keep it in SIL for the life of the plant. Six SIFs are verified end to end with the calculations shown, not just the tool output.

• Write a safety requirements specification that a designer and a verifier can both use
• Select failure-rate data from certificates, OREDA and site records and justify it
• Calculate PFDavg for 1oo1, 1oo2, 2oo3 and mixed architectures including common cause
• Apply hardware fault tolerance and route 1H/2H architectural constraints
• Set proof-test intervals and coverage and see their effect on achieved SIL
• Recognise systematic failure sources and the role of prior-use and certified devices